XDF Post Show

By Gus Lignos, Vice President Sales, MoSys

One of the trends coming out of the recent Xilinx Developer Forum 2019 was about 5G. With South Korea leading the market in 5G base stations and the Olympics soon coming to Japan, there is increasing excitement about the market opportunities for 5G, particularly since it looks like 5G adoption is coming along at a faster clip than LTE adoption did. Xilinx is front and center as their FPGAs are a big part of the solution.

Highlights of this year’s XDF included a very welcomed update on the availability of Xilinx’s impressive 7nm Versal ACAP silicon and the introduction of the Vitis software development environment.

Check this out –directly from the Xilinx blog: “Vitis, a unified software platform that will transform technology innovation. The Vitis unified software platform enables a broad range of developers — including software engineers and AI scientists — to take advantage of the power and adaptability of Xilinx technology in a new and highly efficient way.

Vitis is a major milestone for our platform transformation. Five years in the making and the work of some 800 software engineers, the Vitis unified software platform automatically tailors hardware architecture to the software or algorithmic code, without the need for hardware expertise. Vitis plugs into common software developer tools and utilizes a rich set of optimized libraries, enabling developers to focus on their algorithms and not the hardware underneath.

Victor announced that Vitis will be available to developers for free and general availability will be next month. Vitis is currently shipping to select customers as part of the early-access program for Xilinx Versal series devices. Full details on the Vitis unified software platform, including the press release, are available at the XDF online press kit: https://www.xilinx.com/news/media-kits/xdf-2019.html#vitis

We’re also supporting the developer community with a new site — developer.xilinx.com — that went live today. The new site connects developers to Vitis experts and provides access to a host of resources.”

This strategy speaks strongly to the MoSys mission of providing platform solutions that do not require system architects to recreate their code development. Create it once and you can run it across multiple hardware platforms – in “C” on a CPU, as RTL in an FPGA, or as firmware on the RISC cores embedded in our Programmable HyperSpeed Engine (PHE) device. At XDF, we demonstrated our accelerator technology. We showcased the first offerings from our recently announced IP strategy:  packet forwarding and packet classification firmware as a TCAM alternative running on the 32 RISC cores embedded in our (PHE). The PHE was connected to a Xilinx VU9P UltraScale+ FPGA on a 200G PCIe card we developed in partnership with Xilinx.

If you missed the show, be sure and contact us for a demonstration: Contact Us.