The GigaChip® Interface is a reliable serial chip-to-chip transport protocol that operates over Optical Internetworking Forum (OIF) standard CEI SerDes and achieves 90% efficiency. The protocol, called the GigaChip Interface (GCI), can be scaled to 1, 2, 4 or 8 SerDes lanes as well as multiples of 8s. This IP is available for licencing.
It targets computational and memory solutions with serial interfaces for networking equipment such as MoSys’ Bandwidth Engine® family of ICs. Operating on existing devices with 16 lanes at over 25 Gbps, GCI provides enough bandwidth to support over 10B read/write transactions and sufficient bandwidth to buffer full duplex 400GE. Doubling the pins/lanes or doubling the line rate allows for support of higher bandwidth.
The GigaChip® Interface is groundbreaking technology that has been developed specifically for serial chip-to-chip communications targeting high-speed data applications in growing number of markets such as networking, security, video, and test and monitoring. Founded in July 2010 by MoSys, Inc., GigaChip® Interface has proven interoperability with FPGAs and ASIC/ASSP products from companies including Intel Corporation (Altera), Mellanox (EZ-chip), MoSys, Inc., and Xilinx, Inc.
The GigaChip Interface is high efficiency short-reach, low-power serial interface, intended for chip to chip communication in applications that require fast, highly efficient, reliable transfer of data such as networking. By closely defining the scope and optimizing for memory type transactions, GCI delivers the highest transport efficiency at the lowest protocol latency of any serial interface standard. This enables highly efficient, high-bandwidth, low-latency performance not achievable using currently other serial protocols. The payload granularity of 72 bit, with the CRC and error auto-recovery mechanism ensures the reliability of data transmission. Similar to the fundamental performance breakthrough achieved by the move to double data rate (DDR) style interfaces in the late ’90s, the GigaChip Interface represents the next breakthrough in chip-to-chip communications using differential SerDes technology.
A 16-lane GigaChip Interface can replace up to six separate DDR4 parallel interface busses to memory, which represents a bandwidth density performance increase of 4 times, while reducing system power and interface costs by 2 to 3 times. The pin count benefits can also be achieved when comparing to traditional high speed memories such as SRAM or RLDRAM. Such bandwidth density increases may be required to realize application performance on line cards with aggregate throughput beyond 100G.
The GigaChip Interface has adopted the open OIF CEI and IEEE electrical transport standards making use of this existing electrical ecosystem in order to shorten time to market for the introduction of next generation system designs.
The PHE features four levels of memory, 32 Risc core processors to perform user-programmed In-Memory Functions (IMFs), along with all of the fixed BURST and RMW functions included in the BE3 products. We combine this with our high-speed serial protocol I/O interface to enable your applications to achieve hyperspeed performance.