Why Use SerDes to Talk to Memories? Part 2 of 2
Monday March 29, 2021By Mark Baumann
Director, Product Definition & Applications
MoSys, Inc.
In part one of this blog, we discussed the reasons why designers would not immediately choose this option and the MoSys rationale for architecting a high speed serial I/O device. In part two, we continue to explore the reasons designers are reticent to use SerDes and the technologies that would benefit the most.
To refresh your memory, the reasons designers may not immediately think of SerDes are:
- SerDes are not a “normal” I/O structure used for memories.
- Not familiar with SerDes
- Not sure what benefits SerDes offer
- SerDes are designed for large Packet transfers like E-net, Infiniband, RapidIO, Fibre Channel etc.
- More memory is available on either ASICs or FPGAs
Reason number one was covered in part one of this blog so let’s move on to:
Reason Numbers Two and Three: Not familiar with SerDes and/or Not sure what benefits SerDes has to offer:
The following is a short summary to the benefits of using SerDes as an interface structure:
- All FPGA and ASIC devices support SerDes lanes in ever increasing numbers
- High Speed signaling is supported and has a Roadmap to the future using SerDes
- MoSys has been doing this for a decade now with a track record of Success
- Proven that System Latency is very comparable to that of devices like QDR
- Utilizes fewer pins on the Host device
- Ease of routing on a PCB
- For comparable memory density it requires less system power
- With reduced layout constraints it eases PCB constraints and can help minimize PCB layers
Reason Number Four: SerDes are designed for large Packet transfers like E-net, Infiniband, RapidIO, Fibre Channel, etc.
When designers think SerDes, it is not uncommon for the application to be of high-speed packet transfers across long distance and even across cabling and backplanes. Meaning, something that you would experience in large systems, across backplane and between boxes, either in a building or between buildings. It would also make sense that because the environment is a harsh one, the associated protocols would be robust and built to tolerate transmission errors. If we now take that concept and restrict the environment to a controlled point-to-point on one PCB, the overhead required to ensure a “reliable” transport is GREATLY reduced. In the case of GCI (the MoSys transport protocol), it is 90% efficient for 72bit word transfers. This means that the protocol (which is also a reliable and capable of recovering from transmission faults) transmits 80-bit frames, and 72 bits are data with only 8 bits used to handle the coding needed for error checking and handshaking. It turns out to be a highly efficient protocol as compared to others on the market.
MoSys also can support a design by providing the RTL code to implement the protocol or at least provide sample code for a designer to use as reference for their design.
Reason Number Five: More memory is available on either ASICs or FPGAs
Another common discussion we have with our customers is that they may not need a device like a MoSys Bandwidth Engine because ASICs and FPGAs are being designed with ever increasing amounts of memory on die. This is undeniably true. However, even when placing larger amounts of memory on die, it is more unlikely than likely that the available memory is all that will be needed for the system. When the interface speeds are increasing from Mbits to Gbits and now Tbits, it seems like the amount of needed memory is an ever-moving target. It has been a welcome relief to customers who realize that with as little as 4 SerDes lanes, another supportive memory subsystem can be added to the design.
I have not too often come across a system designers and architects who feel that the amount of memory available on host devices is sufficient to handle everything they wish to include. It is a more common conversation wherein the architect states they will trade off some feature or function to, “fit into” the available resource (quite often that means memory). What I wish to leave you with is the takeaway that with as few as 4 SerDes lanes, it is possible to offer the system a memory that is equivalent in density to 8 QDR devices. Moreover, as a potential option for the design, MoSys solution takes up less board space, is lower power, higher bandwidth, and easier to design onto a PCB.
If any of this is of interest, please contact a MoSys representative to have a more in depth discussion of possibility of using a MoSys Bandwidth Engine device to support additional system features while saving cost, power and utilizing less valuable board real estate.
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