Why Use SerDes to Talk to Memories? – Part 1 of 2

By Mark Baumann Director, Product Definition & Applications

MoSys, Inc.

If a decision needs to be made on what type memory to use in a design, it most likely would not start with a high speed serial I/O device such as SerDes. In part one of this blog, we will discuss the reasons why designers would not immediately choose this option and the MoSys rationale for architecting a high speed serial I/O device. So, first off, there may be some rational reasons as to why the high-speed option is not a first thought and they include:

  1. SerDes are not a “normal” I/O structure used for memories.
  2. Not familiar with SerDes
  3. Not sure what benefits SerDes offer
  4. SerDes are designed for large Packet transfers like E-net, InfinibandRapidIOFibre Channel etc.
  5. More memory is available on either ASICs or FPGAs

If we look at each of these issues, we can try to explain why MoSys feels the Bandwidth Engine families (Quazar, Blazar, PHE) can directly address these issues and explain why the choice was made to develop a High-Speed, High Bandwidth, memory device family.

Reason Number one: SerDes are not a “normal” I/O structure used for memories.

The obvious goal of a memory device is to provide a storage location for data that can be Written, and Read when needed. In some cases, this access is infrequently but in many cases, it is at whatever line rate or throughput rate your system is operating at. The additional concern is that data can be accessed in a totally random fashion, which memory structures like DRAM do not guarantee (without the use of multiple copies that have their own maintenance of continuity issues).

So, let’s presume that the goal is to maintain the access flexibility that we are familiar with, and not have to be concerned with multiple copies. Also, want our design to not being negatively impacted by the use of SerDes as the I/O structure.

When MoSys was in the process of defining the Bandwidth Engine (BE) families, there was a conscious effort to evaluate the speed of product, the required comparable speed of the I/Os to interface with the product and the performance impact of those decisions on the overall access to the memory. As part of the process, it was believed that single-ended I/O structures were approaching a viable end-of-life to run cleanly and reliably at the multiple giga-hertz speed that newer devices would require. The next structure that was considered was SerDes which were cleanly running at up to 10GHz and are today running at greater than 100GHz. This was an obvious answer to the speed concern, and it seemed that the roadmap of SerDes speed was being openly adopted by ASIC and FPGA manufacturers, as this option was felt to provide a clean roadmap to support future-faster devices.

The subsequent actions by OIF and FPGA manufacturers has confirmed that the direction is being adhered to. FPGAs on the market today support 56Gbps SerDes and are planned to support 112 Gbps links. MoSys has devices today that support up to 25Gbps links and can support interfaces that run as high as 400Gbps. Along with the decision to utilize SerDes, MoSys has also developed a GCI (Giga-Chip Interface) protocol to support transfers of individual 72 bit words rather than the kB of data characteristically transferred on SerDes links. Please see data on GCI at the www.mosys.com website. In part two of this blog, we will continue to explore the benefits of SerDes technology and some of the more popular technologies that can gain an advantage from this solution.

If any of this is of interest, please contact a MoSys representative to have a more in depth discussion of possibility of using a MoSys Bandwidth Engine device to support additional system features while saving cost, power and utilizing less valuable board real estate.

Additional MoSys Resources

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