Why is QDR is No Longer the AnswerMonday November 9, 2020
By Mark Baumann
Director, Product Definition & Applications
In the past few years, the memory industry has changed its focus from providing multiple memory options (SRAM (NoBL, ZBT, QDR), Pseudo-Static-SRAM, RLDRAM, Hybrid Memory Cube), to High Bandwidth Memory.
What seems to be available today is different variations on DRAM, DDR4, GDDR, and most notably, High Bandwidth Memory (HBM). The memory industry seems to have refocused efforts on high density and abandoned the need for high random-access rate memory for solutions available either on the FPGA or designed into the ASSP or ASIC. The result seems to be a gap in new products and innovation in the SRAM market.
If we look at QDR, which seems to have been the last innovation in the SRAM market, it has been a decade since this was introduced. The underlying thoughts and technology are also aging with this gap in innovation. Looking at a QDR, it uses high pin count, single-ended LVCMOS type signaling, which requires high complexity PCB layout techniques with densities of only 144Mb or possibly 288Mb. Moreover, it is extremely difficult to place and route multiple devices on a card. And this has a secondary ramification of impacting board space and power.
To address this gap of memory products, MoSys has developed and introduced a family of QPR (Quad Partition Rate) devices. These are devices that range from 576Mb to 1.1Gb in density. Which is 4x to 8x the density of QDR devices. The MoSys devices are monolithic silicon and occupy a fraction of the board space that the equivalent density QDR devices would require.
The other significant improvements that the new QPR devices have introduced is to utilize an I/O technology that uses SerDes rather than single-ended signaling. This benefit is multi-fold in that less pins are utilized on both the host (FPGA) device, while allowing for a roadmap to 25Gbps and higher. It also uses less power than a bus of equivalent bandwidth using LVCMOS pins and makes the board space and routing constraints much easier. All of which helps reduce adoption and development time for a system. In addition to reducing power requirements, that has the effect of reducing the cost of power and cooling requirements.
So, if we are to look at the overall market for High-Speed random access memory devices, there is a decade old QDR device that requires high pin counts, difficult routing, large amounts of board space, high power and cost. Or, there is a new alternative of using a MoSys QPR device that provides minimal pins on the host (in many cases approximately 32 pins), minimal board space (a single package), much simpler routing requirements (allowing up to 8 inches of trace between the host and QPR device), lower power and cost. This is a strong alternative to putting the square peg (DRAM) into the round hole (need for high-speed random-access memory).
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