The Benefits of Serial MemoryWednesday March 25, 2020
By Mark Baumann,
Director of Product Development and Applications
If someone were to suggest that they were looking to develop a high-speed system with need for an associated memory system, I believe your first thoughts would not involve using a SerDes interface. Most people believe that SerDes translates into using a complex interface structure and protocol to communicate. They also believe that in turn, this solution is just too complex for a simple memory interface. Where the goal is to access small 1 to 8 words of data at a time, many of the serial protocols are developed to transfer large Kbytes of data across a backplane or long reach cable. That type of environment is harsh and demands a protocol that can support transmission of large blocks of data in a lossy environment.
If we change the parameters under which we wish to transfer data to:
- Short reach ONLY
- Max of 12 dB of channel loss
- Point-to-point connections only
The problems that previous serial protocols address is much more bounded and greatly reduced. By placing these bounds on the interface, MoSys was able to define a protocol that is light weight (in the required overhead of bits and logic to implement) reliable and acceptable for small word type transfers. (See: Speeding Up Your FPGA/ASIC Memory Interface (GCI)).
If we can agree that there is a possible solution to the protocol overhead issue, then it opens up the other benefits that can arise from the use of SerDes. These being:
- Ability to use a limited and much reduced number of signals to interface with a SerDes rather than an equivalent bandwidth parallel bus
- Ease of routing
- Reduced number of signals and possibly PCB traces
- Ability to place the memory subsystem many inches away from the high-power host controller
- Flexibility of placement of the memory can support a standard rather than exotic thermal solution for cooling. (Improved board thermal profile)
- Quicker PCB Design
When you look at the very basics of a SerDes versus a single-ended I/O there is a tradeoff of wires. Single-ended uses one wire and the SerDes uses 4 – two for Tx and two for Rx since signals are run differentially. You need to run the SerDes at least 4X the speed of the single-ended to have it be of consideration. Luckily, SerDes meets this criterion on the MoSys devices by running at a minimum of 10.3125Gbps which would equate to 2 to 2.5 Gbps on a single ended line and that is NOT what single ended signals re standardly running. They are running in the hundreds of MHz to slightly over 1GHz so running differentially can certainly qualify for meeting the greater than 4X a single-ended transmission rate.
Ease of Routing
In the past few years, with the realization that SerDes are ubiquitous in many systems with many of the system protocols from PCIe Version 4 runs up to 16Gbps) to Ethernet, to Rapid I/O, Interlaken, etc. The use and therefore the ability to route signals that run in the GHz range has become common place. In addition, SerDes interfaces have, in general, not come with a tight a set or routing guidelines (impedance tolerance, length matching, termination, drive distance, etc.) as single-ended signaling. Certainly, both are achievable, but it is simpler to route a much lesser number of higher speed signals versus a large number (100s) of tightly restricted lower speed signals.
Reduced Signal Layers
At MoSys, we have developed several evaluation cards as well as load boards and test vehicles for the Accelerator Engines that we developed. These involved routing traces that ran from a low rate of 10.3125Gbps to upper range of 28 Gbps. On these cards, we have routed the maximum number of traces (which is 32 for Tx and another 32 for Rx), to accomplish this layout the PCB needed just two layers.
In addition to the fact that there are significantly less signals than are needed for QDR type memories, the restrictions on the routing is eased as well. The trace-to-trace and length match and spacing is much less restrictive with a SerDes. The SerDes in the MoSys accelerator Engines can tolerate up to 120UI delta across the 8 lanes of a GCI port.
The end result will be a more cost-effective PCB design.
SerDes are designed to drive over a distance. In the case of the Accelerator Engines they are designed to drive up to a 12 db channel loss. Depending upon the grade of PCB material that is used, this can be anywhere from 6 to 12 inches. This allows for significant flexibility of board layout. If the designer needs to move the memory subsystem away from the host device, due to some other critical routing demands or thermal considerations, allows the board designer the flexibility to do so without impacting performance.
As designers are attempting to integrate everything into fewer and fewer packages in a design, each of those devices are tending to run more cycles at faster rates and this cannot avoid the CV^2F power issue. Each of the high-end devices, be it CPUs, GPUs, ASSPs, ASIC, or FPGA are now doing the job that tens of devices did in the past. The result being that these host devices dissipate a tremendous amount of power. To cool these devices, designers are resorting to exotic solutions from high air flow to some forms of liquid cooling.
This becomes an issue when a support subsystem like memory needs to be close to a device that is dissipating tens to hundreds of Watts of power. The thermal density of the module becomes a cooling challenge.
What is gained by using SerDes is this flexibility to move a critical subsystem (like memory) away from the major thermal source and reduce the thermal density on a PCB design. This can possibly ease the ability to cool the system with traditional less costly methods. This is a secondary effect but one that can have impacts on both reliability and cost.
What I hope is addressed in this blog is the considerations of using a non-conventional interface structure (SerDes) to become a system level benefit to a common design issue.
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