New Quazar Family of High-Speed SRAMs from Mosys Part 1 of 2

By Mark Baumann

Director, Product Definition & Applications

MoSys, Inc.

In Part I of this blog, we will be exploring the architectural features of the newly announced Quazar family of products from MoSys. The Quazar family of parts is designed to address the needs of the next generation high speed Sychronous SRAM and QDR (Quad Data Rate) SRAM market.

MoSys’ goal was to dramatically improve upon the SSRAM/QDR product offerings. The  main attributes to be improved upon being:

  • QDR device densities currently max out at  144Mb (with one offering at 288Mb)
  • Use of wide parallel buses that run at very high frequency
  • Strict rules to layout boards to accept these fast/wide busses
  • Sole Sourced pinouts by existing vendors (Cypress (Infineon) and GSI)
  • No commitment to a future roadmap

So, what MoSys did to address these shortfalls:

  • Introduced devices that are 576Mb and 1.1Gb in density (4-8x the capacity of existing QDR devices)
  • Used a bus structure that is available today and has a growth path to future speed and bandwidth (Since SerDes are becoming more ubiquitous on FPGAs, ASICs and ASSPs this is considered a strong option)
  • Used an open sourced, highly efficient serial protocol to leverage the ever increasing high speed Transceivers on FPGAs/ASICs and reduce layout & routing complexities
  • Guaranteed source of supply (continuity of supply agreement)
  • Similar access rates and system latency at 2-5x faster system access Bandwidth

The MoSys Quazar family device architecture supports the following features:

  • Cell design
  • Bank architecture
  • Partition architecture
  • Quad Partition structure
  • Internal Bus structure
  • Internal clocking and tRC

In Part 2 of this blog, we will start to explore how each of these features support the goal of providing a next generation QDR replacement.

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