Mesochronous Clocking for Low LatencyWednesday September 16, 2020
By Mark Baumann
Director, Product Definition & Applications
The GigaChip Interface (GCI) is designed around a mesochronous — having the same bit rate — of a clock or signal and having the same frequency protocol. It requires that the same clock source be used to clock both transmit and receive devices on a serial link. This type of interface design supports the ability to minimize the overall link latency, by insuring that both ends of the serial link are aligned to a common clock, which insures that the system does not need to build in logic that can compensate for signal or clock drift, over voltage and temperature shifts.
It can also reduce the complexity and power dissipation of the interface and logic on either side of the link. This is similar to the design practice used in Synchronous SRAM designs. In addition to the benefit of minimal latency, this design practice of a common clock to both ends of a link will also ensure that a 0 PPM frequency differential is maintained between the two ends of the link.
In this interface design the SerDes on each end of the link are slightly simplified because they do not need to dynamically adjust for potential frequency drifts. Since the same clock is driving both ends of the link, they will be guaranteed to receive the same clock.
This does not however eliminate the need to be concerned with jitter. It is still necessary to meet the jitter specifications of the interface.
This type of interface has direct benefits to minimizing system latency, by eliminating the need for clock boundary crossings at each end of the SerDes links, which allow the interface to run truly synchronous from end to end. This supports a shortened latency by insuring that even when going off chip to a second device there is no uncertainty in the alignment of signals.
With the help of our partners we have been able to get the added latency through the SerDes interface to be sub 10 clock cycles, which help to bring it close to the latency of a parallel high pin count I/O, which is used on other high speed RAM devices.
The benefit of low latency has been a measurable benefit to using mesochronous clocking and very much worth the incrementally small effort it takes to cleanly route a common clock to both source and destination devices.
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