Expand Your Access to High-Speed Memory on an FPGA

By Mark Baumann

Director, Product Definition & Applications

MoSys, Inc.\

Networks are running at ever increasing speeds these days, creating the need for instantaneous access to data. Overall, it seems that there can never be enough memory. In most FPGA devices, the amount of high-speed, SRAM like memory is now in the 300 to 400Mb range. When this is a desired resource for buffering, tables, statistics, etc., this is rarely adequate. The predominant approach by the FPGA vendors to address this issue has been to attach significant resources of HBM. Although this addresses some memory issues it struggles to support high-speed, random access requirements.

Up to now, the approach to address these issues has been to use QDR SRAM however customers are hitting an issue wherein there is need for additional high-speed, random access memory and the QDR is too shallow, uses too many pins, is difficult to expand. Also, by using multiple devices, the solution draws too much power.

MoSys customers designing accelerator cards that utilize FPGAs have independently come to a conclusion that by using a MoSys device they save on design time, both at the PCB level and the FPGA – RTL level. This is because a MoSys device uses less I/O resource, provides a single device that offers 2 to 4x the onboard FPGA memory resource and 4x to 8 x the attached resource of a QDR type device.

The solution offers a very High-Access Rate Memory designed to compliment and expand the memory resources that are available on an FPGA. It has a very flexible design;  MoSys IP easily integrated with either sample or custom controller code options available. In addition, the solution takes advantage of available SerDes I/O resources in an FPGA or ASIC and helps future proof designs by supporting standard Read-Write memory access and allowing, in a pin compatible package the ability to upgrade with in-memory-functions like burst, ALU (R-M-W) and even an upgrade to a device with 32 RISC cores for custom algorithm deployment.

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