One Device Using 32 I/O Pins that Replaces 4 to 8 QDR Devices
Wednesday August 5, 2020By Mark Baumann
Director, Product Definition & Applications
MoSys, Inc.
The most popular Static device on the market today is a QDR or Quad Data Rate device. It is SRAM that is 144Mb in density (with one option at 288Mb) and uses separate Input and Output bus structures, that run as single ended HSTL bus lines.
To achieve the bandwidth and throughput that the vendors desired, required that the developers and manufacturers of the QDR to utilize separate read and write bus structures. To implement the two busses requires well over 100 signal pins per device. This, in turn, requires the user of this device to route, maintain trace matching, and signal integrity of single ended signals at approx. 1GHz is a very challenging task. All for just 144Mb of storage.
What MoSys has developed, after reviewing the complexities of the QDR device, was to take a very different approach. The initial goals were:
- Much larger density than the SRAM device,
- Improve on signal routing and
- Improved signal integrity issues and
- Meet or better the bandwidth that is achievable with a QDR device.
Out of this effort they MoSys has developed a QPR (Quad Partition Rate) device. The features of it are:
- 4x to 8x the density of a QDR
- Minimum of 2x the bandwidth
- Use SerDes I/Os for ease of layout (32 pins)
- Developed a Low Latency SerDes protocol to address the SerDes overhead issue
If the MoSys QPR devices that are presently available, are considered, the MSQ220 is 576Mb (or 4 x the 144Mb QDR device) and the MSQ 230 device is 1.1Gb (or 8 x the 144Mb QDR device). This directly addresses the first objective in development of the QPR devices.
The second feature, (to attain a minimum of 2x the bandwidth of the present QDR devices) was also achieved. Currently the QRD devices achieve approx. 2B transactions per second and the MSQ220 achieves approximately 4B transactions per second and the MSQ230 achieve approximately 5B transactions per second, again achieving the second of the MoSys objectives.
The third objective was to ease the burden of pins on the host device that talks to a memory and ease the routing concerns for a PCB design, that is required to handle routing of high-speed single ended, trace length matched traces. Because the QDR devices are running signals at approximately 800MHz or higher there are restrictions on how PCB traces can be routed for length, trace to trace differences (both length and spacing), PCB layers to run the signals, and length of traces on the board. All these restrictions or requirement place a burden on the PDB design that can be extremely difficult to insure. In addition, since the devices require greater than 100 signals per device it adds the burden of maintaining all the restrictions across a large swath of the board.
When the QPR devices decided to move the I/Os to SerDes it eased many these burdens. The SerDes I/Os on the QPR devices are capable of auto adaptation. This feature was designed to support driving traces that are up to 10 inches long which provides more placement freedom, it also allows for a lane to lane variation in trace routing of a few inches which will ease PCB issues. The I/Os also support re-ordering which allows for the PCB designer to route the interface as cleanly as possible and the device will (internally) automatically re-order the bit ordering on the bus (so if it is easiest to hook output X of the host to input Y of the QPR device, it is allowed and the QPR device will internally re-order the inputs to align 0 to 0, 1 to 1 etc.) What MoSys believes all this flexibility provides is a quicker, easier, more reliable PCB routing design verses the burdens seen with wide parallel bus schemes, like those on today’s SRAMS.
Another significant benefit of using SerDes, that addresses the third bullet above, is that even after the ease of routing issues, is that for equal or even greater bandwidth, a fraction of the number of pins are needed to transfer the desired data bandwidth. For example, a single QDR device requires greater than 100 pins, with a QPR device with close to 2x the bandwidth only 32 signal pins are required. This is a direct benefit of using differential signaling that can easily run at 4x the signal speed of single ended traces.
I do not wish to infer that SerDes are the perfect answer to interfacing with a memory device. For all of it routing and bandwidth benefits it does carry with it an overhead of needing a protocol for handling all the link training, link recovery and error handling that may occur when running links at 10.3125Gbps, 15Gbps or 25Gbps.
This is the purpose of developing a protocol, which MoSys has called GCI (Giga-Chip Interface) that addresses issues of latency, protocol overhead and link reliability. To get a detailed understanding of the GCI protocol please visit the MoSys website and review the documents listed below. Or contact MoSys Applications and discuss the potential benefits using GCI and Serial can bring to systems.
Additional References
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