At the heart of every Accelerator is the MoSys superior 1T-SRAM memory technology with the industry’s fastest random access rates, single-chip bandwidth and low latency. But, because of In-Memory Functions (IMFs), they have created a whole new type of memory called Accelerator Engines.

In-Memory Function (IMF) Technology

All of our Accelerators use IMFs to perform computing tasks within the memory environment. These functions can either be pre-defined (fixed functions), or they can be programmed by you to fit the specific needs of your application.

Another point of distinction is the type of functions the IMFs perform. Our “BURST” functions are all designed to more efficiently transmit data in and out of the memory environment. Our “RMW” functions perform operations that are common in applications and would usually be performed by the FPGA or processor.

Accelerators and In-Memory Functions (IMFs)

All of our Accelerator ICs are optimized for speed with BURST functions. On top of that, the RMW Accelerators have additional fixed-function IMFs. Our Programmable HyperSpeed Engine (HE) ICs add the capability to program unique IMFs to meet the specific needs of an application.

  Fixed Function
IMFs for Speed
Fixed Function
IMFs for Calculating,
Metering and Statistics
Programmable IMFs
Engine ICs
Programmable HyperSpeed EngineXXX
Bandwidth Engine 3 MacroXX
Bandwidth Engine 2 MacroXX
Bandwidth Engine 3 BurstX
Bandwidth Engine 2 BurstX

SerDes and GigaChip Interface

Enabled by our patented GigaChip, our ICs can get data from the FPGA or processor at rates up to 28Gbps with our HyperSpeed Engine. SerDes technology facilitates the transmission of parallel data between two points over serial streams, reducing the number of data paths and thus the number of connecting pins or wires required. Our Memory ICs are capable of full-duplex operation, meaning that data conversion can take place in both directions simultaneously. 

Multi Port Access

SerDes is moving data simultaneously in both directions. And those 16 lanes are going to multiple ports with multiple GigaChip Interfaces. The enables data to move four times, or in four frames, for each clock cycle. And since we are doing this though only 16 lanes, this high-bandwidth data transmission is done with a reduced number of pins for comparative bandwidth solutions.

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