BURST functions improve the efficiency of data transfers by reducing the number of data commands. In normal operation, every packet of data also has a command, either a request to READ or a request to WRITE. So if two items are transmitted and written to memory only one of them is the actual data you wanted to get there. BURST functions simply bundle multiple packets of data to a single command. If eight data packets would normally also have 8 commands, then it took 16 items of throughput. If you can bundle 8 to a single command then you can move 16 packets of data with just 3 commands.
Using BURST functions, you can nearly double the amount of data going in-and-out of memory utilizing the same amount of bandwidth. After all, what’s the point of having high-bandwidth capability if half the data transferred doesn’t help your application perform functions.
| SerDes Speed Grade | |||
| 10.3125Gbps | 12.5Gbps | ||
| Width | BURST | Throughput (Gbps) | Throughput (Gbps) |
| 16 Lanes | BL8 | 132 | 160 |
| BL4 | 118.8 | 144 | |
| BL2 | 99 | 120 | |
| 8 Lanes | BL8 | 66 | 80 |
| BL4 | 59.4 | 72 | |
| BL2 | 49.5 | 60 | |
| 4 Lanes | BL8 | 33 | 40 |
| BL4 | 29.7 | 36 | |
| BL2 | 24.8 | 30 | |
| SerDes Speed Grade | |||
| 10.3125Gbps* | 12.5Gbps | ||
| Width | BURST | Throughput (Gbps) | Throughput (Gbps) |
| 16 Lanes | BL8 | 132 | 160 |
| BL4 | 118 | 144 | |
| BL2 | 99 | 120 | |
| 8 Lanes | BL8 | 66 | 80 |
| BL4 | 59.4 | 72 | |
| BL2 | 49.5 | 60 | |
| 4 Lanes | BL8 | 33 | 40 |
| BL4 | 29.7 | 36 | |
| BL2 | 24.8 | 30 | |
The PHE features four levels of memory, 32 Risc core processors to perform user-programmed In-Memory Functions (IMFs), along with all of the fixed BURST and RMW functions included in the BE3 products. We combine this with our high-speed serial protocol I/O interface to enable your applications to achieve hyperspeed performance.
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