Bandwidth Engine 2 – RMW Memory IC

The heart of the memory IC is our advanced & parallel array of 1-T SRAM with a capacity of 576Mb.

The tRC is 2.67 ns allowing up to 2.5 billion transactions per second.

The BURST Functions are focused on DATA MOVEMENT to accelerate getting data in and out of the memory faster and more efficiently by reducing the number of command cycles.

The BURST Read/Write In-Memory Functions can combine up to 8 READS and 8 WRITES into a single BURST command. This reduces the number of command cycles when moving data, nearly tripling the amount of data that can be moved in the same timeframe.

The Accelerator Engine can do several BURST Functions simultaneously, further increasing system performance.

MoSys’s Accelerator Engines are designed using 16 SerDes lanes that can transmit data up to 12.5Gbps, with an optional rate of 10Gbps. MoSys’ GigaChip Interface (GCI) delivers  full duplex, CRC protected data throughput, enabling up to 2.5 billion memory transaction per second on as few as 16 SerDes Lanes.

Traditional memory design requires many more interface pins (in some cases 1000s of pins), making signal routing and integrity a design challenge.

Each Accelerator Engine has 2 independent, 8 lane, I/O ports that allow simultaneous memory access operations.

The RMW Functions are focused on DATA COMPUTING where there is need for memory location modification involving RMW in applications such as metering, as well a single or Dual Counter update for statistics.

Traditional memory location modification requires one command to READ a memory location, a second operation to MODIFY the value, and a third command to WRITE the new value back to the memory location.

The RMW Functions provide a least two levels of acceleration. First, the RMW functions can be executed with a single command. Second, since the modification is executed within memory, there is no need to move the data out to be modified, and then back into memory to write. This removes all of the associated I/O latency.