The MSH320 supports the IEEE802.3ba gearbox function. The electrical interfaces support IEEE and OIF-CEI-3.0 10/11G and 25/28G specifications. With the 100G 802.3bj RS-FEC encode, decode and correction functions enabled, the device will encode data into the 4x25G Tx interface and decode and correct data (if needed) from the 4x25G Rx interface.
The IEEE 802.3bj RS-FEC enables additional signal integrity and/or distance capability over optical or copper interconnects and has been specified in multiple standards and MSAs including 100GBASE-SR4, CWDM4 and PSM4. The device can also be configured as a 10 lane retimer. In this mode, the device can support up to 10 independent 10G to 11G interfaces for Ethernet or OTN. This allows low-cost FPGAs with sub-25Gb/s interfaces to support QSFP28-based optical modules requiring RS-FEC.